View HYM71V16C735HCT8M-H_2905936.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

16mx72 bits pc133 sdram registered dimm with pll, based on 16mx8 sdram with lvttl, 4 banks & 4k refresh this document is a general product description and is subject to change without notice. hyundai electronics does not assume any responsibility for use of circuits described. no patent licenses are implied. rev. 0.1/may.01 hym71v16c735hct8m series description the hynix hym71v16c735hct8m series are 16mx72bits ecc synchronous dram modules. the modules are composed of nine 16mx8bits cmos synchronous drams in 400mil 54pin tsop-ii package, one 2kbit eeprom in 8pin tssop package on a 168pin glass-epoxy printed circuit board. one 0.22uf and one 0.0022uf decoupling capacitors per each sdram are mounted on the pcb. the hynix hym71v16c735hct8m series are dual in-line memory modules suitable for easy interchange and addition of 128mbytes memory. the hynix hym71v16c735hct8m series are fully synchronous operation referenced to the positive edge of the clock . all inputs and outputs are synchronized with the rising edge of the clock input. the data paths are internally pipelined to achieve very high bandwidth. features ? pc133/pc100mhz support ? 168pin sdram registered dimm ? serial presence detect with eeprom ? 1.125? (28.56mm) height pcb with double sided components ? single 3.3 0.3v power supply ? all device pins are compatible with lvttl interface ? data mask function by dqm ? sdram internal banks : four banks ? module bank : one physical bank ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? programmable burst length and burst type - 1, 2, 4 or 8 or full page for sequential burst - 1, 2, 4 or 8 for interleave burst ? programmable cas latency ; 2, 3 clocks ordering information part no. clock frequency internal bank ref. power sdram package plating hym71v16c735hct8m-k 133mhz 4 banks 4k normal tsop-ii gold HYM71V16C735HCT8M-H
pc133 sdram registered dimm rev. 0.1/may.01 3 hym71v16c735hct8m series pin description pin pin name description ck0~ck3 clock inputs the system clock input. all other inputs are registered to the sdram on the rising edge of clk cke0 clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh /s0, /s2 chip select enables or disables all inputs except ck, cke and dqm ba0, ba1 sdram bank address selects bank to be activated during /ras activity selects bank to be read/written during /cas activity a0 ~ a11 address row address : ra0 ~ ra11, column address : ca0 ~ ca9 auto-precharge flag : a10 /ras, /cas, /we row address strobe, column address strobe, write enable /ras, /cas and /we define the operation refer function truth table for details rege register enable register enable pin which permits the dimm to operateion in buffered mode when rege input is low, in registered mode when rege input is high dqm0~dqm7 data input/output mask controls output buffers in read mode and masks input data in write mode dq0 ~ dq63 data input/output multiplexed data input / output pin cb0 ~ cb7 check bit input/output check bits for ecc vcc power supply (3.3v) power supply for internal circuits and input buffers v ss ground ground scl spd clock input serial presence detect clock input sda spd data input/output serial presence detect data input/output sa0~2 spd address input serial presence detect address input wp write protect for spd write protect for serial presence detect on dimm nc no connection no connection
pc133 sdram registered dimm rev. 0.1/may.01 4 hym71v16c735hct8m series pin assignments front side back side front side back side pin no. name pin no. name pin no. name pin no. name 1 vss 85 vss 41 vcc 125 *ck1 2 dq0 86 dq32 42 ck0 126 nc 3 dq1 87 dq33 43 vss 127 vss 4 dq2 88 dq34 44 nc 128 cke0 5 dq3 89 dq35 45 /s2 129 nc 6 vcc 90 vcc 46 dqm2 130 dqm6 7 dq4 91 dq36 47 dqm3 131 dqm7 8 dq5 92 dq37 48 nc 132 nc 9 dq6 93 dq38 49 vcc 133 vcc 10 dq7 94 dq39 50 nc 134 nc architecture key 51 nc 135 nc 52 cb2 136 cb6 11 dq8 95 dq40 53 cb3 137 cb7 12 vss 96 vss 54 vss 138 vss 13 dq9 97 dq41 55 dq16 139 dq48 14 dq10 98 dq42 56 dq17 140 dq49 15 dq11 99 dq43 57 dq18 141 dq50 16 dq12 100 dq44 58 dq19 142 dq51 17 dq13 101 dq45 59 vcc 143 vcc 18 vcc 102 vcc 60 dq20 144 dq52 19 dq14 103 dq46 61 nc 145 nc 20 dq15 104 dq47 62 nc 146 nc 21 cb0 105 cb4 63 nc 147 rege 22 cb1 106 cb5 64 vss 148 vss 23 vss 107 vss 65 dq21 149 dq53 24 nc 108 nc 66 dq22 150 dq54 25 nc 109 nc 67 dq23 151 dq55 26 vcc 110 vcc 68 vcc 152 vcc 27 /we 111 /cas 69 dq24 153 dq56 28 dqm0 112 dqm4 70 dq25 154 dq57 29 dqm1 113 dqm5 71 dq26 155 dq58 30 /s0 114 nc 72 dq27 156 dq59 31 nc 115 /ras 73 vcc 157 vcc 32 vss 116 vss 74 dq28 158 dq60 33 a0 117 a1 75 dq29 159 dq61 34 a2 118 a3 76 dq30 160 dq62 35 a4 119 a5 77 dq31 161 dq63 36 a6 120 a7 78 vss 162 vss 37 a8 121 a9 79 *ck2 163 *ck3 38 a10/ap 122 ba0 80 nc 164 nc 39 ba1 123 a11 81 wp 165 sa0 40 vcc 124 vcc 82 sda 166 sa1 voltage key 83 scl 167 sa2 84 vcc 168 vcc note : * ck1 ~ ck3 are connected with termination r/c (refer to the block diagram)
pc133 sdram registered dimm rev. 0.1/may.01 5 hym71v16c735hct8m series block diagram note : 1. the serial resistor values of dqs are 10ohms 2. the padding capacitance of termination r/c for ck1~ck3 is 12pf
pc133 sdram registered dimm rev. 0.1/may.01 6 hym71v16c735hct8m series serial presence detect byte number function description function value note -k -h -k -h byte0 # of bytes written into serial memory at module manufacturer 128 bytes 80h byte1 total # of bytes of spd memory device 256 bytes 08h byte2 fundamental memory type sdram 04h byte3 # of row addresses on this assembly 12 0ch 1 byte4 # of column addresses on this assembly 10 0ah byte5 # of module banks on this assembly 1 bank 01h byte6 data width of this assembly 72 bits 48h byte7 data width of this assembly (continued) - 00h byte8 voltage interface standard of this assembly lvttl 01h byte9 sdram cycle time @/cas latency=3 7.5ns 7.5ns 75h 75h byte10 access time from clock @/cas latency=3 5.4ns 5.4ns 54h 54h byte11 dimm configuration type ecc 02h byte12 refresh rate/type 15.625us / self refresh supported 80h byte13 primary sdram width x8 08h byte14 error checking sdram width x8 08h byte15 minimum clock delay back to back random column address tccd = 1 clk 01h byte16 burst lenth supported 1,2,4,8,full page 8fh 2 byte17 # of banks on each sdram device 4 banks 04h byte18 sdram device attributes, /cas lataency /cas latency=2,3 06h byte19 sdram device attributes, /cs lataency /cs latency=0 01h byte20 sdram device attributes, /we lataency /we latency=0 01h byte21 sdram module attributes registered/buffered inputs, with pll 1fh byte22 sdram device attributes, general +/- 10% voltage tolerence, burst read single bit write, precharge all, auto precharge, early ras precharge 0eh byte23 sdram cycle time @/cas latency=2 7.5ns 10 75h a0h byte24 access time from clock @/cas latency=2 5.7ns 6 54h 60h byte25 sdram cycle time @/cas latency=1 - - 00h 00h byte26 access time from clock @/cas latency=1 - - 00h 00h byte27 minimum row precharge time (trp) 15ns 20ns 0fh 14h byte28 minimum row active to row active delay (trrd) 15ns 15ns 0fh 0fh byte29 minimum /ras to /cas delay (trcd) 15ns 20ns 0fh 14h byte30 minimum /ras pulse width (tras) 45ns 45ns 2dh 2dh byte31 module bank density 128mb 20h byte32 command and address signal input setup time 1.5ns 1.5ns 15h 15h byte33 command and address signal input hold time 0.8ns 0.8ns 08h 08h byte34 data signal input setup time 1.5ns 1.5ns 15h 15h byte35 data signal input hold time 0.8ns 0.8ns 08h 08h byte36 ~61 superset information (may be used in future) - 00h byte62 spd revision intel spd 1.2a 12h 3, 8 byte63 checksum for byte 0~62 - 9fh e0 byte64 manufacturer jedec id code hynix jeded id adh byte65 ~71 ....manufacturer jedec id code unused ffh byte72 manufacturing location hsi(korea area) hsa (united states area) hse (europe area) hsj (japan area) asia area 0*h 1*h 2*h 3*h 4*h 10
pc133 sdram registered dimm rev. 0.1/may.01 7 hym71v16c735hct8m series byte number function description function value note -k -h -k -h byte73 manufacturer?s part number (component) 7 (sdram) 37h 4, 5 byte74 manufacturer?s part number (128mb based) 1 31h 4, 5 byte75 manufacturer?s part number (voltage interface) v (3.3v, lvttl) 56h 4, 5 byte76 manufacturer?s part number (memory width) 1 31h 4, 5 byte77 ....manufacturer?s part number (memory width) 6 36h 4, 5 byte78 manufacturer?s part number (module type) c (rcc registered with pll) 43h byte79 manufacturer?s part number (data width) 7 37h 4, 5 byte80 ....manufacturer?s part number (data width) 3 33h 4, 5 byte81 manufacturer?s part number (refresh, sdram bank) 5 (4k refresh, 4banks) 35h 4, 5 byte82 manufacturer?s part number (manufacturing site) h 48h 4, 5 byte83 manufacturer?s part number (generation) c 43h 4, 5 byte84 manufacturer?s part number (package type) t 54h 4, 5 byte85 manufacturer?s part number (component configuration) 8 (x8 based) 38h 4, 5 byte86 manufacturer?s part number (low profile) m 4dh 4, 5 byte87 manufacturer?s part number (hyphen) - (hyphen) 2dh 4, 5 byte88 manufacturer?s part number (min. cycle time) k h 4bh 48h 4, 5 byte89 ~90 manufacturer?s part number blanks 20h 4, 5 byte91 revision code (for component) process code - 4, 6 byte92 ....revision code (for pcb) process code - 4, 6 byte93 manufacturing date work week - 3, 6 byte94 ....manufacturing date year - 3, 6 byte95 ~98 assembly serial number serial number - 6 byte99 ~125 manufacturer specific data (may be used in future) none 00h byte126 reserved 100mhz 64h 7, 8, 9 byte127 reserved refer to note7 8fh 7, 8, 9 byte128 ~256 unused storage locations - 00h continued 10. refer to hsi web site. 9. these values are applied to pc100 applications only per intel pc sdram specification. 8. refer to the most recent intel and jedec spd specification 7. ck0 connected to dimm, tbd junction temp, cl2(3) support, intel defined concurrent auto precharge support 6. not fixed but dependent 5. basically hynix writes part no. except for ?hym? in byte 73~90 to use the limited 18 bytes from byte 73 to byte 90 4. ascii adopted 3. bcd adopted 2. 1, 2, 4, 8 for interleave burst type 1. the bank address is excluded note :
pc133 sdram registered dimm rev. 0.1/may.01 8 hym71v16c735hct8m series absolute maximum ratings note : operation at above absolute maximum rating can adversely affect device reliability. dc operating condition (t a =0 to 70 c ) note : 1.all voltages are referenced to v ss = 0v 2.v ih (max) is acceptable 5.6v ac pulse width with <=3ns of duration. 3.v il (min) is acceptable -2.0v ac pulse width with <=3ns of duration. ac operating test condition (t a =0 to 70 c , v dd =3.3 0.3v, v ss =0v) note : 1.output load to measure access times is equivalent to two ttl gates and one capacitor (50pf). for details, refer to ac/dc outpu t load circuit parameter symbol rating unit ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ 125 c voltage on any pin relative to v ss v in , v out -1.0 ~ 4.6 v voltage on v dd relative to v ss v dd, v ddq -1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1 w soldering temperature time t solder 260 10 c sec parameter symbol min typ max unit note power supply voltage v dd , v ddq 3.0 3.3 3.6 v 1 input high voltage v ih 2.0 3.0 v ddq + 0.3 v 1,2 input low voltage v il -0.3 0 0.8 v 1,3 parameter symbol value unit note ac input high / low level voltage v ih / v il 2.4/0.4 v input timing measurement reference level voltage vtrip 1.4 v input rise / fall time tr / tf 1 ns output timing measurement reference level voltage voutref 1.4 v output load capacitance for access time measurement c l 50 pf 1
pc133 sdram registered dimm rev. 0.1/may.01 9 hym71v16c735hct8m series capacitance (ta=25 c , f=1mhz) output load circuit parameter pin symbol -k/h unit min max input capacitance ck0 c i1 - 30 pf cke0 c i2 - 15 pf /s0, /s2 c i3 - 15 pf a0~11, ba0, ba1 c i4 - 15 pf /ras, /cas, /we c i5 - 15 pf dqm0~dqm7 ci 6 - 15 pf data input / output capacitance dq0 ~ dq63 c i/o - 15 pf vtt =1.4v rt=250 w 50 pf output 50 pf output dc output load circuit ac output load circuit
pc133 sdram registered dimm rev. 0.1/may.01 10 hym71v16c735hct8m series dc characteristics i (ta=0 to 70 c , v dd =3.3 0.3v) note : 1.v in = 0 to 3.6v, all other pins are not tested under v in =0v 2.d out is disabled, v out =0 to 3.6 dc characteristics ii note : 1. i dd1 and i dd4 depend on output loading and cycle rates. specified values are measured with the output open 2. min. of trrc (refresh ras cycle time) is shown at ac characteristics ii 3. all values are measured with registered and pll parameter symbol min. max unit note input leakage current i li -10 10 ua 1 output leakage current i lo -1 1 ua 2 output high voltage v oh 2.4 - v i oh = -4ma output low voltage v ol - 0.4 v i ol = +4ma parameter symbol test condition speed unit note -k -h operating current i dd1 burst length=1, one bank active t rc 3 t rc (min), i ol =0ma 1400 1400 ma 1 precharge standby current in power down mode i dd2p cke v il (max), t ck = 15ns 338 ma i dd2ps cke v il (max), t ck = 169 precharge standby current in non power down mode i dd2n cke 3 v ih (min), cs 3 v ih (min), t ck = 15ns input signals are changed one time during 30ns. all other pins 3 v dd -0.2v or 0.2v 440 ma i dd2ns cke 3 v ih (min), t ck = input signals are stable. 270 active standby current in power down mode i dd3p cke v il (max), t ck = 15ns 280 ma i dd3ps cke v il (max), t ck = 110 active standby current in non power down mode i dd3n cke 3 v ih (min), cs 3 v ih (min), t ck = 15ns input signals are changed one time during 30ns. all other pins 3 v dd -0.2v or 0.2v 570 ma i dd3ns cke 3 v ih (min), t ck = input signals are stable. 220 burst mode operating current i dd4 t ck 3 t ck (min), i ol =0ma all banks active cl=3 1500 1500 ma 1 cl=2 1700 1700 auto refresh current i dd5 t rrc 3 t rrc (min), all banks active 5500 ma 2 self refresh current i dd6 cke 0.2v 430 ma
pc133 sdram registered dimm rev. 0.1/may.01 11 hym71v16c735hct8m series ac characteristics i (ac operating conditions unless otherwise noted) note : 1. in registered dimm, data is delayed an additional clock cycle due to the register (this is, device cl + 1 = dimm cl) 2. assume tr / tf (input rise and fall time ) is 1ns, if tr & tf > 1ns, then [(tr+tf)/2-1]ns should be added to the parameter 3. access times to be measured with input signals of 1v/ns edge rate, from 0.8v to 2.0v if tr > 1ns, then (tr/2-0.5)ns should be added to the parameter parameter symbol -k -h unit note min max min max system clock cycle time cas latency = 3 tck3 7.5 1000 7.5 1000 ns 1 cas latency = 2 tck2 7.5 10 ns clock high pulse width tchw 2.5 - 2.5 - ns 2 clock low pulse width tclw 2.5 - 2.5 - ns 2 access time from clock cas latency = 3 tac3 - 5.4 - 5.4 ns 3 cas latency = 2 tac2 - 5.4 - 6 ns data-out hold time toh 2.7 - 2.7 - ns data-input setup time tds 1.5 - 1.5 - ns 2 data-input hold time tdh 0.8 - 0.8 - ns 2 address setup time tas 1.5 - 1.5 - ns 2 address hold time tah 0.8 - 0.8 - ns 2 cke setup time tcks 1.5 - 1.5 - ns 2 cke hold time tckh 0.8 - 0.8 - ns 2 command setup time tcs 1.5 - 1.5 - ns 2 command hold time tch 0.8 - 0.8 - ns 2 clk to data output in low-z time tolz 1 - 1 - ns clk to data output in high-z time cas latency = 3 tohz3 2.7 5.4 2.7 5.4 ns cas latency = 2 tohz2 2.7 5.4 3 6 ns
pc133 sdram registered dimm rev. 0.1/may.01 12 hym71v16c735hct8m series ac characteristics ii note : 1. timing delay due to the register is considered in a registered dimm 2. a new command can be given trrc after self refresh exit parameter symbol -k -h unit note min max min max ras cycle time operation trc 60 - 65 - ns auto refresh trrc 60 - 65 - ns ras to cas delay trcd 15 - 20 - ns ras active time tras 45 100k 45 100k ns ras precharge time trp 15 - 20 - ns ras to ras bank active delay trrd 15 - 15 - ns cas to cas delay tccd 1 - 1 - clk write command to data-in delay twtl 0 - 0 - clk 1 data-in to precharge command tdpl 1 - 1 - clk 1 data-in to active command tdal 4 - 5 - clk 1 dqm to data-out hi-z tdqz 2 - 2 - clk 1 dqm to data-in mask tdqm 0 - 0 - clk mrs to new command tmrd 2 - 2 - clk precharge to data output hi-z cas latency = 3 tproz3 4 - 4 - clk 1 cas latency = 2 tproz2 3 - 3 - clk power down exit time tpde 1 - 1 - clk self refresh exit time tsre 1 - 1 - clk 2 refresh time tref - 64 - 64 ms
pc133 sdram registered dimm rev. 0.1/may.01 13 hym71v16c735hct8m series device operating option table hym71v16c735hct8m-k HYM71V16C735HCT8M-H note : dimm/cas latency = device cl + 1 (registered mode) cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 2clks 2clks 6clks 8clks 2clks 5.4ns 2.7ns 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns cas latency trcd tras trc trp tac toh 133mhz(7.5ns) 3clks 3clks 6clks 9clks 3clks 5.4ns 2.7ns 125mhz(8ns) 3clks 3clks 6clks 9clks 3clks 6ns 3ns 100mhz(10ns) 2clks 2clks 5clks 7clks 2clks 6ns 3ns
pc133 sdram registered dimm rev. 0.1/may.01 14 hym71v16c735hct8m series command truth table note : 1. exiting self refresh occurs by asynchronously bringing cke from low to high 2. x = don t care, h = logic high, l = logic low. ba =bank address, ra = row address, ca = column address, opcode = operand code, nop = no operation command cken-1 cken cs ras cas we dqm addr a10/ ap ba note mode register set h x l l l l x op code no operation h x h x x x x x l h h h bank active h x l l h h x ra v read h x l h l h x ca l v read with autoprecharge h write h x l h l l x ca l v write with autoprecharge h precharge all banks h x l l h l x x h x precharge selected bank l v burst stop h x l h h l x x dqm h x v x auto refresh h h l l l h x x burst-read-single- write h x l l l h x a9 pin high (other pins op code) self refresh 1 entry h l l l l h x x exit l h h x x x x l h h h precharge power down entry h l h x x x x x l h h h exit l h h x x x x l h h h clock suspend entry h l h x x x x x l v v v exit l h x x
pc133 sdram registered dimm rev. 0.1/may.01 15 hym71v16c735hct8m series package demension note : 1. tolerances on all dimensions +/-5 (0.127) unless otherwise specified. 2. thickness includes plating and / or metallization . 85 168 1 84 5250(133.35) 5013.78(127.35) 1700(43.18) 1450(36.83) 2150(54.61) 450(11.43) 250(6.35) 700(17.78) 157.48(4.0) 1125(28.56) " c" " b" " a" 4550(115.57) detail "b" detail "a" 5.9(0.15) 100(2.54) min. 39.37(1.0) 50(1.27) 78.74(2.0) 39.37(1.0) detail "c" 78.74(2.0) 122.83(3.12) 39.37(1.0) 125(3.175) 125(3.175) unit: mil (mm) * (1 mil = 1/1000 inches) r78.74 (2.0) r78.74 (2.0) ( front side) ( rear side) 50(1.27) 157.48(4.0) min. 320(8.13) max.

▲Up To Search▲

Price & Availability of HYM71V16C735HCT8M-H

	To Download HYM71V16C735HCT8M-H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .